Dielectric structures in solar cells

ABSTRACT

A dielectric, structure and a method of forming a dielectric structure for a rear surface of a silicon solar cell are provided. The method comprises forming a first dielectric layer over the rear surface of the silicon solar cell, and then depositing a layer of metal such as aluminum over the first dielectric layer. The metal layer is then anodized to form a porous layer and a material layer is deposited over a surface of the porous layer such that the material deposits on the surface of the porous layer without contacting the silicon surface.

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TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to the field of devicefabrication and, in particular, to the formation of a structure thatassists light trapping in solar cells.

BACKGROUND OF THE INVENTION

The fabrication of solar cell semiconductor devices typically involvesthe formation of metal contacts to a p-n junction device. Thesemiconductor material (e.g., silicon) absorbs light and generateselectron and hole carriers which can then be separated by the p-njunction in the device. Majority carriers (e.g., electrons in n-typesemiconductor material) are collected by the metal contacts which areformed to both the p-type and n-type material of the device. Incommercially-produced screen-printed silicon solar cells, the n-typemetal contacts are formed by screen printing and subsequently firing asilver paste in a grid pattern over the front (illuminated side) of thedevice. The p-type contact is formed by screen-printing the entire rearp-type surface of the device with an aluminium paste. This paste, whenfired at temperatures of 780-870° C., forms a back-surface field (BSF)which reduces the recombination of the electron minority carriers (in ptype material) at the silicon-metal interface and enables the collectionof the hole majority carriers.

Screen-printed silicon solar cells have been industrially-produced for25-30 years with continued improvements driving efficiencies towards17-18% and 16-17% for mono-crystalline and multi-crystalline wafersubstrates, respectively. One of the limitations of screen printed solarcells is that screen printed metal fingers formed on the illuminatedsurface of the solar cell effectively shade the cell and thus limit thegeneration of carriers in the cell. One way to address this issue hasbeen to place all the metal contact regions on the rear surface of thecell. Such rear contact cells have been successfully manufactured,however although efficiencies as high as 24% have been achieved in aproduction environment, these rear contact technologies typically resultin a higher cost per Watt of power generated than the less efficientcommercially-produced screen-printed silicon solar cells. The highercost of manufacture arises from the more complex processing required andthe need to use higher quality silicon wafers to ensure that carriersgenerated towards the front (illuminated) surface of the solar cell cantravel to a rear junction to be collected by the metal contacts.

Clearly what are required are new cost-effective manufacturing processeswhich can be applied to less-expensive, and potentially lower lifetime,silicon substrates in order to reduce the cell conversion costs of rearcontact cells and make them more commercially competitive with existingscreen-printed technology.

SUMMARY

According to one aspect a method of forming a dielectric structure for arear surface of a silicon solar cell is provided, the method comprising:

-   -   i) forming a first dielectric layer over the rear surface of the        silicon solar cell;    -   ii) depositing a layer of metal over the first dielectric layer;        and    -   iii) anodising the metal layer to form a porous layer.

According to a second aspect a silicon solar cell is provided includinga dielectric structure on a rear (non-illuminated) surface of the solarcell, the dielectric structure comprising:

-   -   i) a first dielectric layer over the rear surface of the silicon        solar cell; and    -   ii) a porous layer of anodized metal over the first dielectric        layer.

Preferably, a layer of material is subsequently deposited over a surfaceof the porous layer. The material deposited over the surface of theporous layer may seal the pores of the porous layer to trap air in thepores of the porous layer or alternatively the material may be depositedto extend into the pores as well as over the surface of the porouslayer.

The first dielectric layer may cover a part or all of the rear surfaceof the silicon solar cell. Similarly the metal layer may cover a part orall of the dielectric layer.

The metal layer may comprise one of aluminium, titanium, magnesium,zinc, niobium or tantalum but will preferably comprises aluminium.

The first dielectric layer may comprise one or more of silicon dioxide,silicon nitride, silicon carbide, silicon oxynitride and amorphoussilicon.

The layer of material deposited over the surface of the porous layer maycomprise a dye, reflective particles or light scattering nanoparticles.The material deposited over the surface of the porous layer may furthercomprise a polymer encapsulant and the dye, reflective particles orlight scattering nanoparticles may be loaded into the polymerencapsulant and the polymer encapsulant applied over the porous materialand into the pores of the porous material. The layer of materialdeposited over the surface of the porous layer may also comprise adopant source.

Alternatively the layer of material deposited over the surface of theporous layer may comprise a metal layer which is deposited over theporous layer and within the pores of the porous layer without contactingthe silicon surface.

After formation of the porous layer it may be locally meltedperiodically at points where contact is to be made to the underlyingsilicon, whereby the porous layer and underlying first dielectric layerare disrupted and the underlying silicon is exposed and doped withaluminium. The disruption and doping is preferably performed with alaser.

When the material deposited over the surface of the porous layer is ametal layer, it may also form a metal contact layer which contacts thedoped silicon via the disruption in the porous layer and underlyingfirst dielectric layer. The metal contact layer may be formed to contacta base of a front junction solar cell, a rear junction solar cell or arear junction solar cell.

The silicon solar cell may advantageously comprise a semiconductorsubstrate havening a thickness of less than 200 micron. The wafers usedfor this method will typically be in the range of 120-180 μm thick, andmore preferably 150-160 μm thick. The method is particularlyadvantageous when the semiconductor device is a solar cell, particularlya rear junction solar cell.

Metal electrodes may also be formed to contact a plurality ofsemiconductor regions of the silicon solar cell, in which case themethod further comprises:

-   -   i) depositing a polymer layer on the rear surface of the solar        cell in a pattern corresponding to a desired metal isolation        pattern;    -   ii) depositing the metal layer as a conductive metal contact        layer over the rear surface to contact the plurality of        semiconductor regions of the solar cell;    -   iii) processing the polymer layer to disrupt the conductive        metal contact layer in the pattern of the polymer layer to        isolate metal of the conductive metal contact layer contacting        different ones of the plurality of semiconductor regions.

The step of processing the polymer layer may involve subjecting thedevice to ultrasonic excitation within a liquid. The polymer layer maybe soluble in an organic solvent in which case the liquid will comprisethe solvent, however the polymer layer may also be soluble in water inwhich case the liquid will comprise at least 10% water. The processingstep may also involve heating the semiconductor device to soften or meltthe polymer layer.

The polymer layer is preferably applied by a printing device, such as aninkjet printing device or an aerosol jet printing device.

The metal contact layer may be for example applied by sputtering orthermal evaporation and preferably comprises aluminium. The metalcontact layer is preferably formed on a non-illuminated surface of thesolar cell and contacts two semiconductor regions of two differentsemiconductor polarities of the solar cell.

According to a third aspect a method of forming an electrical contactfor a solar cell device is provided, the method comprising:

-   -   a) forming a metal layer over the rear surface of the device;    -   b) selectively anodising regions of the metal layer to form at        least one insulating region and at least one metal region,        whereby the at least one metal region forms the electrical        contact of the device.

The metal layer may be selectively anodised by covering the metal layerwith a masking material that is resistant to an anodising solution usedto anodise the metal. The covering material my be used to prevent areasof metal underlying the masking material from being anodised whereby theareas of metal underlying the masking material are retained as the atleast one metal region. The masking material may be a polymer and may bedeposited using a printing method comprising one of screen printing,inkjet printing or aerosol printing.

Alternatively, the masking material may be an inorganic dielectriccomprising one of silicon dioxide, titanium dioxide, silicon nitride,silicon oxynitride, silicon carbide, or aluminium oxide. The inorganicdielectric layer is deposited as a layer and may be patterned using anetching process.

Isolating polymer lines may be deposited on the rear surface of thesolar cell device before the layer of metal is deposited and then afterthe metal layer is formed the device may be processed to lift-off themetal above the polymer lines and thus form a plurality of isolatedregions in the metal layer.

An anodic potential may be applied to a subset of the plurality ofisolated metal regions during the anodisation process resulting in theat least one insulating region and the at least one metallic regions.

The method as claimed wherein the selective anodising step forms aplurality of metal regions separated by the at least one insulationregion. The solar cell device may be a rear contact solar cell device inwhich case at least one of the plurality of metal regions may contact ap-type semiconductor region of the solar cell device and at leastanother one of the plurality of metal regions may contact an n-typesemiconductor region of the solar cell device. The solar cell device mayalso comprise a plurality of photovoltaic devices, in which case theplurality of metal regions may comprise a metal region in contact with ap-type semiconductor region of one solar cell device and a n-typesemiconductor region of an adjacent photovoltaic device to create aseries connection of the adjacent photovoltaic devices. The metal layermay comprise aluminium, titanium, magnesium, zinc, tantalum, or niobiumand preferably comprises aluminium.

In the case where the solar cell device is a silicon solar cell, anamorphous silicon passivating layer may be formed on the rear surface ofthe solar cell device before forming the aluminium layer over the rearsurface of the solar cell device. After the selective anodisation stepthe aluminium and underlying amorphous silicon layer may be heated,where contact is required between the silicon solar cell and theremaining aluminium not anodized in the selective anodisation step, tocause metal induced crystallisation of the amorphous silicon.

The metal layer may be formed by printing using a colloidal metal ink.After printing the colloidal metal ink it may be fired to make itconductive.

According to a fourth aspect, a method of forming an anodised metaloxide layer on a surface of a semiconductor device is provided,comprising:

-   -   a) printing a metal layer using a colloidal metal ink;    -   b) firing the printed a metal layer to make it conductive; and    -   c) anodising the metal layer to form the anodised metal oxide.

The printed metal layer may be formed in a pattern by selectivelyprinting the rear surface of the device.

The printed metal layer may cover an area of the semiconductor devicewhere metal contacts are not required such that metal contacts areformed in areas not covered by printed metal or the anodised metaloxide. In this case a corrosive nickel ink may be deposited in the areasnot covered by printed metal or the anodised metal oxide and thecorrosive nickel ink may then be fired to create a nickel seed layeronto which metal contacts are plated.

The metal particles in the colloidal metal ink may be less than 2 um indiameter and may be printed using area aerosol deposition heads. Theprint head may print lines which are 0.5 to 3 cm wide and preferably 1.0to 2.0 cm wide. The printing speed may be used to control the thicknessof the deposited colloidal metal ink.

The colloidal metal ink may also be printed using screen printing orinkjet printing with appropriate adjustments to the viscosity of theink.

After printing, the deposited colloidal metal ink may be sintered at atemperature between 150 and 500° C. and preferably at a temperaturebetween 180 and 220° C. (nominally 200° C.).

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of a solar cell rear contact and its method of formationwill now be described, by way of example, with reference to theaccompanying drawings in which:

FIG. 1A is a schematic diagram showing a rear contact cell design;

FIG. 1B is a schematic diagram showing a variation of the rear contactcell design of FIG. 1A in which grooves are patterned prior to a firstdiffusion process;

FIG. 2 is a process flow diagram showing the basic steps for fabricatingthe rear contact cell design of FIG. 1A;

FIG. 3 is a schematic showing the placement of the isolation patternwith respect to the p-type and n-type openings on the rear surface ofthe design of FIG. 1A;

FIG. 4A is a graphical representation drawn from a Dektak profile of asection of an isolation pattern formed by printing a novolac resin usingan aerosol jet printer.

FIG. 4B is a graphical representation drawn from a Dektak profile of asection of an isolation pattern formed by printing a water solublepolymer, such as polyacrylamide (PAA), using an aerosol jet printer.

FIG. 4C is a diagrammatic sectional side view of a portion of the deviceof FIG. 1A showing an isolation pattern formed by printing novolac resinusing an aerosol jet printer.

FIG. 4D is a diagrammatic sectional side view of the portion of thedevice of FIG. 1A after the novolac resin layer has been removed to forman isolation pattern in an overlying metal layer.

FIG. 4E is a diagrammatic sectional side view of a portion of the deviceof FIG. 1A showing an isolation pattern formed by printing awater-soluble polymer, such as PAA, using an aerosol jet printer.

FIG. 4F is a diagrammatic sectional side view of the portion of thedevice of FIG. 1A after the water-soluble polymer layer has been removedto form an isolation pattern in an overlying metal layer.

FIG. 5 is a process flow diagram showing the steps for forming apatterned n-type rear emitter for the variation shown in FIG. 1B;

FIG. 6 is an illustration of an anodic aluminium oxide layer withmetallised pores;

FIG. 7 is a process flow diagram showing a variation of the processdepicted in FIG. 2, in which the p+ doping is achieved by laser-dopingthrough an anodic aluminium oxide layer.

FIG. 8 is a schematic diagram showing a variation of the rear contactcell design of FIG. 1A made by employing the process of FIG. 7;

FIG. 9 is a process flow diagram showing a variation of the processdepicted in FIG. 7, in which the process of FIG. 5 is also incorporated.

FIG. 10 is a schematic diagram showing a variation of the rear contactcell design of FIG. 1A made by employing the process of FIG. 9;

FIG. 11 is a schematic diagram showing a variation of the rear contactcell depicted in FIG. 10 in which both front and rear contacts areemployed;

FIG. 12 shows an isolation pattern for forming a single aluminium layerpatterned into metallic and insulating regions in a cell similar to thatseen in FIG. 11;

FIG. 13 shows the aluminium layer of FIG. 12 patterned into twoelectrically isolated regions, one of which has been anodised to form adielectric region;

FIG. 14 shows a sectional elevation view of a part of the cell of FIG.12 before the aluminium 1 is patterned;

FIG. 15 shows the cell of FIG. 14 after the aluminium is patterned andpartially anodized;

FIG. 16 shows a sectional elevation view of a part of the cell similarto the cell of FIGS. 4C & 4D when employing the single aluminium layermethod used in the cell of FIGS. 12 to 15 shown before the aluminium ispatterned; and

FIG. 17 shows the cell of FIG. 16 after the aluminium is patterned andpartially anodized.

FIGS. 18, 19, 20, 21 & 22 illustrate a method of forming patternedmetallic and insulating/light trapping regions from a single layer ofmetal in a cell similar to the cell of FIG. 10 in which FIG. 18 shows asectional elevation view of the first step of metal layer formation;

FIG. 19 shows the sectional elevation view of the device of FIG. 18after a masking layer has been applied;

FIG. 20 shows the sectional elevation view of the device of FIGS. 18 &19 after a masking layer has been selectively opened;

FIG. 21 shows the sectional elevation view of the device of FIGS. 18, 19& 20 after a selective anodising step;

FIG. 22 shows the device of FIGS. 18, 19, 20 & 21 in plan view showingthe metallisation and insulation pattern;

FIGS. 23, 24, 25, & 26 illustrate a method of forming metallic andinsulating/light trapping regions from a single layer of printed metalin which FIG. 23 shows a sectional elevation view after the first stepof printing a patterned metal layer;

FIG. 24 shows the sectional elevation view of the device of FIG. 23after the printed metal layer has been fired to make the metal layerconductive;

FIG. 25 shows the sectional elevation view of the device of FIGS. 23 &24 after a metal seed layer has been formed as a precursor to platingcontacts to semiconductor regions of the device: and

FIG. 26 shows the sectional elevation view of the device of FIGS. 23, 24& 25 after an anodising step and plating of the contacts constrained bythe anodised layer.

DETAILED DESCRIPTION OF EMBODIMENTS

Fabrication of low-cost solar cell devices requires processes which canminimise material usage and/or utilise, where possible, less expensivematerials. For screen-printed solar cells, the cost of silicon waferswill continue to dominate the cost of devices even though large costsavings have been made in cell conversion costs over the past 5-10years. Processes which can enable the use of thinner wafers cansignificantly reduce the cost of final devices. Furthermore, thinnerwafers, if well passivated, can result in higher energy conversionefficiencies due to a reduction in the dark saturation current. Theprocess of screen printing can result in high breakage rates as thewafer thickness reduces to values of ˜160 μm and therefore this presentsa limit to how thin wafers can ultimately be for the currently dominantpatterning and metallisation process. If further gains are to be madewith respect to using even thinner silicon substrates then alternativemethods of patterning are required which place less stress on thesubstrates (i.e., contactless methods).

A further factor which currently limits cell conversion costs forscreen-printed silicon solar cells is the cost of the silver metal usedto form the front-metal contact grid. Currently the silver pastecontributes ˜40% of the cell conversion cost and this cost fraction mayincrease as the price of silver continues to increase partly due todemand driven by the increase in manufacture of screen-printed siliconsolar cells. Clearly, this situation is not sustainable if photovoltaicsare to provide an increasing fraction of the world's electricity needsin the future. The development of new low-cost technologies that uselower cost metals such as aluminum or copper would be advantageous.Aluminum is particular attractive due to its low cost (˜US$2.60 per kgcompared to >US$1000 per kg for silver), reasonably low resistivity(2.65×10⁻⁶ Ωcm at 20° C.), ready availability and ability to form aprotective native oxide barrier.

However, aluminium's propensity to readily oxidize makes it moredifficult to formulate into printable conductive inks that can bedeposited using contact-free methods such as inkjet or aerosol printing.Consequently aluminium is typically best deposited using processes suchas sputtering and thermal evaporation if contact of processing equipmentwith the substrate is to be avoided. Another potential issue with usingaluminium to contact silicon directly is that silicon can diffuse intoaluminum at reasonably low temperatures and cause aluminium spiking.This failure mode has been observed in integrated circuit devices,however it can be largely eliminated by adding small amounts of siliconto the aluminium (e.g., 0.5-2% and preferably ˜1% Si).

A final strategy to reduce the cost of solar cells devices is toincrease the efficiency of devices and thus increase the power outputper manufactured device. In addition to reducing the cost per Watt ofthe module, the balance of systems costs is also reduced. Cellefficiency can be increased by attempts to minimise sources of loss.Current screen-printed solar cells can experience shading losses of 5-6%due to the presence of the metal grid on the illuminated surface of thecell. By placing both polarity metal contacts on the rear surface theselosses can be avoided. However, typically solar cell devices whichemploy a rear junction to collect the light-generated carriers haveneeded to use higher quality and therefore more expensive(higher-lifetime) silicon wafers in order to enable carriers generatedat the illuminated side of the cell to travel to the rear surface to becollected.

Some cell design technologies, such as emitter wrap-through (EWT) ormetal-wrap-through (MWT), attempt to address this problem by eitherhaving the rear emitter layer or the rear metal layer of the solar cellwrapping through the device to the front surface in order to moreeffectively collect carriers. The “wrapping” is typically achieved usinga laser to form holes or grooves which extend from the back to the frontof the solar cell. To some extent these technologies have enabled rearmetal contacting of cells fabricated on commercial-grade silicon wafers,however neither of the technologies have been widely adopted forcommercial manufacture to-date most likely due to their resultingefficiency gains being insufficient to warrant the increased complexityof the manufacturing process. Furthermore, cost-effectiveimplementations of EWT and MWT technologies often employ screen-printedmetallisation and therefore are limited to wafer thickness above 160 μm.

However, some manufacturers (e.g., SunPower) have demonstrated thatefficiencies exceeding 24% can be achieved in a manufacturingenvironment with a rear emitter, rear contact cell design which does notrequire extensive laser patterning in order to enable the capture ofcarriers generated close to the front surface. Instead they usehigh-lifetime silicon substrates, good surface passivation, andwell-engineered ohmic contacts to achieve high efficiencies incommercial production. However this comes at a cost and the cost perWatt of produced cells still significantly exceeds that of currentcommercially-produced screen-printed cells.

A large advantage could be obtained if processing techniques could bedeveloped to enable higher minority effective carrier lifetimes to beachieved using lower-quality commercial-grade silicon substrates. Ifcell thicknesses are reduced then the criticality of ensuring goodsurface passivation increases. Using dielectrics such as silicon nitrideand silicon oxynitride, which are routinely deposited using plasmaenhanced chemical vapor deposition (PECVD), n-type silicon surfaces canbe well passivated with surface recombination velocities less than 100cm/s being reported. The low surface recombination velocities arelargely due to the formulation of an accumulation layer in the n-typesilicon formed because of the existence of stored positive charges inthe dielectric layer. This accumulation layer serves to repel minoritycarrier holes from the surface and therefore minimise surfacerecombination. Typically, p-type silicon is more difficult to passivatebecause the minority carriers are the more mobile electrons and henceare more difficult to eliminate from surface regions, althoughdielectrics such as aluminium oxide have been shown to passivate thesesurfaces well. Also dielectric layers such as silicon nitride andsilicon oxynitride deposited onto p-type silicon can result in theformation of inversion layers which can minimise surface recombinationdue to the very low hole concentration at the surface, however formingmetal contacts to p-type silicon through such layers can be difficultdue to shunting between the inversion layer and the metal contact.

A further advantage of placing both polarities of metal contacts on therear surface is that the cell interconnection process can be simplified.For commercially-produced screen-printed solar cells, interconnectionsmust be formed from the n-type contacts on the illuminated surface tothe p-type contacts on the rear surface. This necessitates theinterconnect wire being looped between the front and rear surfaces,placing limitations on how closely individual cells can be placed in amodule and resulting in possible shunting if the interconnect wire comesinto contact with the side of the cell. Interconnection becomes morestraightforward if both polarity contacts are on the rear surface andtherefore, although new rear contact strategies such as EWT and MWT mayoffer only modest improvements in cell efficiency over screen-printedcells, further cost benefits may result during module fabrication.

Many rear-contact cell designs employ n-type wafers due to their higherminority carrier lifetimes, however most advances that are occurring inlower-cost wafer manufacture are being applied to boron-dopedsubstrates. Boron, unlike phosphorus, has a high segregation coefficientand therefore large variations in resistivity do not occur as crystalsgrow. An example of new wafer substrate technology that will most likelyresult in lower-cost and potentially higher lifetime p-type wafers isthe cast mono-silicon technology where substantially mono-crystallinesilicon can be grown in a cast similar to the way in whichmulti-crystalline ingots are currently gown. The resulting p-typesilicon does not contain the same high levels of oxygen that exist in CZp-type mono-crystalline silicon and so higher minority lifetimes arepossible due to the absence of boron-oxygen defects. The use of p-typewafers is also preferable for commercial production because an emittercan be formed using the safer and more established process of phosphorusdiffusion. Boron diffusions require the use of toxic gases such as borontribromide, higher diffusion temperatures and require careful processcontrol for reproducible results.

For the above reasons the preferred arrangement for the currentfabrication process uses p-type wafers, though clearly similar low-cost,low-waste, low stress (or touch free) processes could also be applied ton-type wafers. FIG. 1A schematically illustrates a device 100incorporating a first rear contact design. A p-type wafer 110 ofresistivity 1-3 Ωcm is enshrouded with an n-type diffusion, which has asheet resistance of 100-300 Ω/sq (ohms/square) and more preferably,150-200 Ω/sq on the front surface 115 and ˜25 Ω/sq on the rear surface120. Although not depicted in FIG. 1A for simplicity, both the front andrear surfaces of the wafer are textured to reduce reflection and enhancelight trapping within the cell. The lightly-doped front surface layer115 forms a floating junction which acts to reduce recombination at thefront surface by reducing the concentration of holes at that surface.Under illumination this floating junction becomes forward-biased andinjects electrons into the p-type bulk where they diffuse down aconcentration gradient to the rear-surface n-type metal contacts.

Grooves in the rear surface contact a heavily-doped p-type region 130that is formed only at the base of the grooves. A dielectric layer 125,preferably comprising silicon nitride, is formed on both the front andrear surface of the wafer to a thickness of 70-80 μm and preferably74-76 nm. In a variation of the preferred cell design the siliconnitride layer is deposited over a thin silicon dioxide layer 126 ofthickness 10-15 nm. The silicon nitride dielectric layer providesexcellent surface passivation for the entire n-type surface.

Openings are then formed in the dielectric layer 125 to exposeheavily-doped n-type silicon 140 and heavily-doped p-type silicon 145.To increase processing throughput these openings are preferably grooveopenings having a width of 15-30 μm and more preferably ˜20 μm.Alternatively, these openings can be hole openings to further reduce themetal-silicon interface area. A layer of aluminium is then depositedover the entire rear surface to form metal contacts via the formedopenings. The n-type and p-type contacts are isolated from each otherusing a lift-off technique to create openings 160. This isolationtechnique is described in more detail below with reference to FIGS. 2, 3& 4A to 4F.

FIG. 1B depicts a variation of the cell design 100 where grooves arefirst patterned through a masking oxide layer such that the phosphorusdiffusion process results in heavily-doped n-type silicon (i.e., 25 Ω/sqsheet resistance) only within the grooves and a lighter diffusionelsewhere. This variation has the advantage that it removes theheavily-doped layer from the rear surface (resulting in reduced darksaturation current) and places the n-type contacts closer to the frontsurface floating junction thus reducing the distance that the minoritycarriers must travel to be collected. However, these advantages areobtained at a cost of additional processing which is discussed furtherbelow with reference to FIG. 5.

The preferred arrangement will now be described with reference to theprocess flow 200 in FIG. 2. Wherever possible, wet chemical anddiffusion processes are performed as currently done in commercialproduction of screen-printed solar cells. Incoming wafers, which arepreferably <100> p-type wafers, are textured in step 205 using atexturing process such as the alkaline texturing process currently usedin the manufacture of mono-crystalline screen-printed silicon cells. Thewafers can be pseudo square commercial-grade p-type. CZ silicon wafers,or more preferably good quality cast mono-crystalline square wafers. Thewafers are preferably 120-180 μm thick, and more preferably 150-160 μmthick. Alternative texturing processes, such as acidic texturing canalso be used in step 205.

After cleaning using a standard metal clean in 2% HF and 4% HCl and arinse in deionised water, the wafers are subjected to phosphorusdiffusion in step 210. Preferably, the phosphorus diffusion is performedusing a POCl furnace, with the wafers being placed in the boat so as toonly lightly-diffuse the front surface to ˜120-300Ω/sq, and morepreferably 150-200 Ω/sq, while heavily-diffusing the rear surface to15-45 Ω/sq (or approx. ˜25 Ω/sq). After diffusion, the phosphorous isdriven-in during a wet thermal oxidation step (step 215), resulting in asilicon dioxide layer of thickness ˜200 nm. Alternatively, an in-linebelt diffusion process can be used to perform the phosphorus diffusion.

In step 220 grooves are etched in the rear surface using alow-temperature patterned etching step such as described in PCTPublication WO2009/094711 (PCT/AU2009/000098) “Method for patternedetching of selected material”, where locally-formed HF etches thesilicon dioxide to leave openings in the dielectric layer. Preferably,the acid source for this process is provided by first non-contactprinting an acidic water soluble polymer such as polyacrylic acid (PAA)and then overprinting the fluoride source. Both printing steps can beachieved using a fluid deposition device such as an inkjet printer or anaerosol jet printer, although use of an aerosol printer is preferredbecause of the ability to remove a larger amount of the solvent duringthe deposition process. This is particularly advantageous for theprinting of the PAA where additional solvent (water) can cause spreadingof the deposited aerosol when it contacts the silicon dioxide surface.

For the PAA deposition, an ultrasonic atomizer is preferably used with atransducing voltage of 45 V and atomizer temperature of 25° C. toatomise a 5% (w/v) solution of PAA in water. A single pass using a 200μm deposition tip can be used to deposit lines of dried PAA on thesilicon dioxide surface of the wafer which is held by vacuum to a platenheated to between 50 and 60° C., and more preferably 55° C. Preferablythe atomizer and sheath flow rates used are 15-25 and 20-25 cm³/minute(ccm), respectively, although other higher aerosol flow rates can beused if more. PAA is required to be deposited. Higher sheath flow ratescan be used to constrain the PAA printed line width and thus enablenarrower etched lines. The process velocity used is between 5 and 15mm/s, and more preferably 10 mm/s.

The fluoride source is provided by a 10% (w/v) ammonium fluoridesolution which is also atomized using an ultrasonic atomizer with atransducing voltage of 40 V and atomizer temperature of 25° C. Thedeposition of the fluoride source is aligned by point and lineregistration to the printed PAA and preferably 2 printing passes aremade using a 100 μm deposition tip while the wafer is held to the platenwhich is heated to between 40 and 60° C., and more preferably 50° C.Preferably the atomizer and sheath flow rates used are 15 and 10 ccm,respectively, although as described for the PAA deposition these flowrates can be varied to achieve different deposition properties.Furthermore different deposition tip sizes can also be used to depositmore or less aerosol if required.

Deposition of the polymer and fluoride sources can be achieved on oneprinting station where the wafers are transported from the polymer tothe fluoride printing head assembly using a wafer transport systemcomprising a moving belt platen. Each printing head assembly cancomprise an array of nozzles with the nozzle spacing corresponding tothe spacing (pitch) of the required grooves. Preferably, all the nozzlesare connected to a single atomiser unit and aerosol and sheath gas flowsare maintained constant for all the nozzles in the array. Alternatively,each nozzle can be supplied by its own atomiser unit and parameters foreach atomiser units can be individually controlled. The latterarrangement has advantages for variations where different patterning maybe desirable across individual wafers. For example, if wider grooves aredesired then higher aerosol flow rates can be used.

In order to achieve wafer processing throughputs of 1500 or 3000 wafersper hour, respectively, multiple printing lanes each with their ownprinting head assemblies can be arranged. Each printing lane has its ownautomated wafer loading system which places wafers on the moving vacuumplaten. Software-controlled visual alignment systems are used toregister the location of placed wafers and adjust the position andalignment angle of the deposition head assembly with respect to thewafer.

After deposition has been completed the wafers are rinsed in deionisedwater for 5 mins. This rinse step is preferably performed in a separateinline rinse step. A key advantage of the patterning process 220 is thatbecause small amounts of PAA and fluoride are used in the patterningprocess the concentration of these chemicals is very low in the rinsingbath enabling long rinse bath lifetime and reduced waste management. Theconcentration of fluoride in the bath can be managed and maintainedbelow 5 ppm enabling the minimal waste treatment as the bath isconstantly bled and re-filled.

In a variation to the preferred process, the acidic polymer can bespin-coated or spray-coated over the entire wafer surface to bepatterned to form a dried polymer layer which is between 1 and 2.5 μm,and more preferably between 1.5 and 2.0 μm thick. Although thisvariation can increase processing throughput, it has the disadvantage ofusing more polymer than is strictly required by the etching process. Italso can result in shorter rinse bath lifetime.

Ideally the acid and fluoride deposition conditions are varied toachieve etched line widths of 50-120 μm and more preferably of 65-75 μm.While the silicon dioxide mask is still in place, the silicon at thebase of the grooves is preferably etched in 20% (w/v) KOH for 20 mins at80° C. to etch grooves which are 25-35 μm deep and 20-75 μm wide, andmore preferably 15-30 μm wide, at the base of the grooves. Acidicetching in solutions comprising an oxidant (such as nitric acid) andhydrofluoric acid can also be used to form the grooves, however theisotropic nature of these etchants can result in more “balloon” shapedgrooves. The tapered grooves that result from the use of anisotropicalkaline etchants can help constrain the etching (by directing the flowof deposited aerosol) when openings are made through the dielectriclayer in step 245 of process 200.

These grooves enable the base metal contact for the solar cell, howeverthey also eliminate potential shunting between the n-type emitter at therear of the cell and the base contact and enable clear alignmentfeatures when opening the dielectric within the heavily-doped regions instep 245. A common problem experienced with interdigitated rear contactcells is shunting between the n-type and p-type regions. This problem isof particular concern when a heavily-doped region of one polarity isrequired to be formed through an emitter layer of the other polarity asthe doping process has to compensate and overwhelm the presence of theother polarity dopant. By displacing the heavily-doped p-type regionaway from the rear surface emitter this problem can be effectivelyeliminated.

Doping of the regions at the base of the grooves is preferably achievedby printing lines of aluminium ink (such as provided by AppliedNanotech) and sintering at temperatures exceeding the eutectictemperature of aluminium of 577° C. Preferably a spike fire is performedwith a temperature of 750-800° C., and more preferably 775-785° C. beingmaintained for 1 min. Fast ramp down times will prevent aluminiumdiffusion from the p+ regions formed during cooling of the molten alloy.In a variation to this doping process, washed and dried fine aluminiumwire containing 0.5-2% (preferably ˜1%) silicon and having a diameter of20 μm can be placed in the formed grooves and fired in essentially thesame way as described above for the aluminium ink. Cassette-mediatedmethods of loading the grooves with the cleaned, pre-cut fine wire canenable fast throughput, however care must be taken to ensure that thewire is maintained straightened else misalignment can occur.

With both the aluminium ink and the fine aluminium wire approaches to p+doping at the base of the grooves, un-reacted aluminium can optionallybe removed before proceeding to step 235 of process 200 by immersingwafers in a solution comprising 10% hydrochloric acid for durations of1-2 mins depending on the volume of metal deposited in the grooves. Thisfurther treatment ensures that only the p+ silicon remains in thegrooves and therefore smaller metal silicon contact areas can be achievein step 245 of process 200.

The p+ doping can also be achieved by printing solutions containingdoped silicon nanoparticles such as those produced by companies likeInnovalight. These inks can be doped with any p-type dopant and so highdoping levels can be achieved. Aluminium has a limited solid solubilityin silicon so doping achieved by aluminium alloying processes asdescribed above are limited to achieving dopant levels of ˜2×10¹⁸ cm⁻³.Heavier doping of the p-type region results in increased tunneling atthe metal semiconductor interface and hence lower contact resistance.The doped silicon nanoparticles can be printed using a range of fluiddeposition devices included inkjet and aerosol jet printers. Industrialprinting devices enable accurate registration of printing with featureson the substrate (typically within 5-10 μm) and the patterned groovesare clearly visible as registration features in alignment camerastypically used for these devices.

In a further variation to the doping process in step 230, a borondiffusion process can be performed in a diffusion furnace to form the p+regions. Wafers must be diffused for ˜1 hour at 900° C. and then thedopants driven in for up to 2 hrs at 1050° C. in order to form veryheavily-doped p+ regions. Although able to form a heavily-doped uniformp+ layer, the boron diffusion is undesirable because of the need to usesuch high temperatures which is undesirable for maintaining reasonableminority carrier lifetimes in lower-quality silicon materials.

In yet another variation to the p-type doping process, a layer ofaluminium can be deposited (e.g., by thermal evaporation or sputtering)over the rear surface and fired substantially as was described for theAl ink. The patterning oxide layer which is formed in step 215 providesa barrier to aluminium and silicon diffusion over the rear surface andso aluminium alloying only occurs in the regions of the openings in theoxide layer 145. The aluminium layer is then removed as described forthe oxide layer below.

The formation of a p+ region at the base of the grooves is essential forensuring low contact resistance. If the p-type silicon is doped to alevel exceeding 10¹⁸ cm⁻³ then significant tunneling can occur throughthe metal-semiconductor barrier enabling ohmic contact. As the dopantconcentration approaches 10¹⁹ cm⁻³ then charge transport becomesdominated by tunneling and the specific contact resistivity can fall tovalues of ˜10⁻⁶ Ωcm². If cell performance is to be enhanced by reducingthe area that metal (aluminium in this case) contacts the silicon thenthe criticality of low specific contact resistivities increases.

After the formation of p+ regions at the base of the grooves, in step235 the masking silicon dioxide is removed by immersing the cell in abuffered oxide etch or dilute HF solution. A dielectric layer 125 isdeposited in step 240. In the preferred arrangement, a silicon nitridelayer is deposited using PECVD onto a cleaned silicon surface.Preferably the silicon nitride layer has a thickness of ˜75 nm and arefractive index of ˜2.0. In a variation to this process, the siliconnitride layer can be deposited over a thin silicon dioxide layer whichhas been formed using either a thermal oxidation process, a wet chemicalprocess involving immersion in sulphuric acid solutions or azeotropicnitric acid solutions (substantially as described in “Nitric acidpretreatment for the passivation of boron emitters for n-type basesilicon solar cells” by Mihailetchi et el. in Appl. Phys Lett., 92,063510, 2008) or by a PECVD deposition.

Surface recombination is an important factor in the cell design andsurface recombination velocities of, less than 100 cm/s are desirable.In addition, to providing excellent surface recombination via reducingsurface state defects and formation of an accumulation layer in then-type layer, silicon nitride deposited by PECVD is rich in hydrogenthat can help passivate impurities and crystal impurities in the bulk ofthe wafer on annealing. The silicon nitride is preferably deposited at atemperature of 400° C. and is subsequently annealed at 680° C. for 10mins in forming gas (5% H₂ in N₂ or Ar).

The formation of all the heavily-doped p-type and n-type regions beforethe deposition of the passivating dielectric layer is advantageous inthat hydrogen that is introduced into the cell as part of thepassivation layer deposition is not driven out by subsequenthigh-temperature processes. Hydrogen is extremely mobile in silicon andeven local high temperature treatments, such as laser-doping, can impactsignificantly on the hydrogen passivation achieved from hydrogen-richlayers deposited by PECVD. As a result, very high minority carrierlifetimes and hence open circuit voltages can be achieved in finaldevices. These high lifetimes are especially important for rear contactdevices because they enable minority carriers to diffuse to the rearemitter for collection and hence minimise the requirement to use veryhigh quality substrates.

In step 245, openings are etched in the dielectric layer 125 using thepatterned etching method described earlier for step 220. In thispatterning process, groove or hole openings as narrow as 10-30 μm andmore preferably ˜20 μm are etched in the dielectric layer 125 for n-type(140) and p-type (145) metal contacts. Although hole openings can reducethe metal-silicon interface area and hence the dark saturation currentof the final device, they are more difficult to achieve at industrialthroughput rates so groove openings are preferably used.

Since the dielectric layer 125 is only 75 nm thick openings in thislayer can be achieved in two fluoride printing passes. A singledeposition head assembly can print the etching pattern for each of then-type and p-type openings, with a second identical deposition headassembly printing the second pass. Following etching, wafers are rinsedas described for step 220.

The final steps enable the formation of low-cost aluminium metalcontacts through the formed openings for each of the embodimentsdescribed herein. Isolation of the n-type and p-type contacts isachieved using a lift-off technique. First in step 250 a polymer 405 (inFIG. 4C) is printed according to an isolation pattern 350 (as shownschematically in FIG. 3) on the rear surface of the cell. The rearsurface of the solar cell 300 is shown with regions exposed in thedielectric 125 for n-type contacts 310 and p-type contacts 320. Theisolation pattern 350 is printed such that all the connected n-typeregions are isolated from all the connected p-type regions. Theisolation pattern 350 is positioned where a discontinuity in a rearaluminium layer would be required in order to effect electricalisolation of the n-type and p-type contacts. In the preferredarrangement the pitch between each of the n-type (and also each of thep-type grooves) is between 0.5 and 2 mm and more preferably 1 mm. Thoughclearly other pitch values can also be used with closer spacing beingadvantageous in variations where a more lightly-doped emitter layer 115is employed.

Preferably, the polymer that is used is a novolac resin dissolved in ahigh vapor pressure solvent such as sulfolane at a concentration of 1 to12% (w/v), and more preferably 3-5% (w/v). The polymer can be printedusing any non-contact printing devices (e.g., drop-on-demand andcontinuous inkjet printers, aerosol jet printer, and jetting/dispensingdevices used for dispensing of high viscosity materials such as pastesand adhesives), however due to the use of aerosol jet printingtechnology in other steps, the preferred arrangement employs thattechnology for the printing of the isolation pattern. Deployment of alimited number of different technologies enables manufacturers todevelop expertise in those technologies and be more effective atmaintaining and refining processes with time.

The isolation pattern can be represented by a single tool path which canbe printed/dispensed very quickly preferably in a single pass. The widthof the printed polymer is preferably 70-200 μm and more preferably ˜100μm wide to ensure reliable lift-off performance. In general, the maximumnecessary height of the printed isolation pattern is between 1-2 timesthe thickness of the metal layer that is to be isolated provided thatthe printer surface is not highly textured. Isolating metal layers onwafers having texture patterns with large differences in feature sizes(e.g., alkaline texturing with large pyramid sizes or remainingsaw-damage marks) makes it desirable that the height of the printedpolymer be ˜5 times higher than the thickness of the metal layer.

The novolac resin is preferably dispensed using a pneumatic atomizer ofan aerosol printer with sheath, aerosol, and impact exhaust flow ratesof 30, 1930 and 1900 ccm, respectively. However, other depositionsettings can also be used in order to achieve printed lines with theappropriate shape to enable sufficient lift-off. The platen temperatureis maintained at between 90 and 150° C., and more preferably 120° C. inorder to evaporate solvent from the printed lines after deposition.Using these deposition conditions, dried polymer lines of width 100-150μm and height 1 to 20 μm can be formed depending on the number of layersdeposited. Deposition of 2 layers of 4% (w/v) novolac resin in sulfolaneusing a deposition speed of 2 mm/s results in dried polymer lines 405 of110-120 μm width and 6 μm maximum height on an alkaline textured wafersurface, as shown in the surface profile illustrated graphically in FIG.4A and diagrammatically in FIG. 4C. Deposition of further layers canresult in thicker lines an easier (i.e., quicker) aluminium lift-off.

Other resins or polymers can also be used with a range of differentsolvents. If the polymers are jetted using a printing device such as anaerosol jet printer, then preferably high vapor pressure solvents areused in order to prevent excessive drying of particles which can resultin overspray of aerosol particles at the edges of the printed lines. Hotmelt waxes can also be used, provided that they can be reliablydispensed on the surface according to the isolation pattern. Hot meltwaxes have been successfully dispensed by inkjet printers for selectiveemitter patterning for silicon solar cells by inkjet printing systemssuch as manufactured by Schmid.

Water soluble polymers, such as PAA, can also be used to form theisolation pattern with water being used as the solvent. The watersolubility of these polymer systems is advantageous with respect towaste management, however typically a larger number of layers arerequired in order to form a dried polymer line 406 of sufficient heightfor lift-off. Furthermore these polymers can result in dried polymerlines which exhibit high outer ridges regions with a centralvalley/depression due to the movement of the deposited polymer moleculesto the edge of the printed lines where evaporation is enhanced (see thesurface profile illustrated graphically in FIG. 4B and diagrammaticallyin FIG. 4E). The profile of the printed lines can be varied to minimizethis effect by increasing the platen temperature and also “drying” theaerosol further (e.g., by using lower aerosol flow rates and highersheath gas flow rates) to eliminate excess solvent. However, the shapeof the printed polymer profile does not appear to affect the lift offsignificantly as long as the maximum height of the printed line issufficiently high to initiate the lift-off process.

Polyacrylic acid can be deposited as the lift-off polymer using theprinting conditions outlined previously. When a 1% (w/v) PAA solution isatomized as described for step 220 and deposited on an alkaline texturedsurface maintained at a temperature of 50° C., dried polymer lines withprofiles as shown in FIG. 4B and FIG. 4E result. On average, the driedpolymer height at the edges and centre of the deposited lines is ˜6 μmand 3.5 μm, respectively. No further heat treatment is required for thedried polymer lines. The printing of further layers results in the shapeof the printed lines becoming higher and more parabolic. Once 10 layersof the isolation pattern are deposited the line profile is parabolic andthe lines are 10-12 μm high.

In step 255, aluminium layer 150 is then either thermally-evaporated orsputtered over the entire rear surface including over the printedisolation lines 310, 405, 406. Preferably, an aluminium layer 150 havinga thickness of 1-3 μm and more preferably 1.0-2.5 μm is formed. Thedeposited aluminium layer 150 needs to be sufficiently thick to ensurethat series resistance of the metal contacts is sufficiently low.Clearly thicker layers may be required for larger wafers, especially ifthe contacting pattern shown in FIG. 3 is used. This aluminium layercontacts both the heavily-doped n-type silicon 120 and the heavily-dopedp-type silicon 130 via the openings 140 and 145, respectively. Dependingon the way in which interconnection is achieved for the cells when theyare incorporated into modules, it can be necessary to increase thealuminum thickness in the busbar (side) regions of the cell's n-type andp-type metal contacts. These regions will effectively carry the currentfor entire cell and so resistance in these regions must be minimised tomaximise cell and module efficiency.

In order to prevent aluminium spiking, which is caused by the diffusionof silicon into the aluminium at relatively low temperatures, preferably0.5 to 2% and more preferably ˜1% silicon is added to the aluminium thatis evaporated or sputtered over the surface. The small amount of addedsilicon does not alter the conductivity of the aluminium layersignificantly, with the resistivity reducing by 0.7 μΩcm for 1% addedsilicon. If further safeguards against aluminium spiking are required(e.g., if final devices are to operated at higher temperatures) then adiffusion barrier layer comprising a silicide, nitride, carbide or acombination thereof can be deposited before aluminium deposition.

For example, the specific contact resistivity for aluminium contacts toheavily-doped silicon can reduced to values less than 10⁻⁶ Ωcm² by usinga nickel silicide intervening layer. Before Ni deposition by sputtering,wafers are immersed in 1% hydrofluoric acid for 20 s to remove anynative oxide in the openings. A layer of nickel of thickness of ˜50 nmis then sputtered over the rear surface from a 99.99% pure sputteringtarget and then subsequently annealed at 350° C. for 2 to 20 mins andmore preferably 5 mins. Aluminium is then deposited by sputtering orevaporation. Un-reacted nickel can optionally be removed by immersion ina 20-35% (w/v) solution of nitric acid before aluminium deposition.

In the preferred arrangement, where the polymer lines comprise driedresin 405, cells are sonicated in an ultrasonic bath using a frequencyof ˜40 kHz in for 10-15 mins in acetone at 20-25° C., to remove thealuminium formed over the isolation pattern formed by the dried resinlines 405 to create isolation openings 160 (see FIG. 4D). Preferablycells are arranged in a polypropylene cassette and oriented parallel tothe base of the ultrasonic bath during the sonication process. They arethen rinsed in deionised water for 5 mins to remove all traces ofacetone and aluminium particles before being dried in readiness for celltesting and interconnection. Aluminium can be readily reclaimed from thesonication waste. This reclaiming of aluminium is especiallystraightforward when water-soluble polymers (e.g., such as PAA) are usedfor forming the isolation pattern.

Shorter sonication times can be employed by either forming thickerpolymer lines or using less-textured surfaces. For example, for anacidic textured silicon surface 100% removal of 1.5 μm thick aluminiumover the isolation pattern can be readily achieved by printing a singlelayer of resin and sonicating in acetone at 20-25° C. for 10-15 mins.Due to the reduced processing costs of the in-line acidic texturingcompared to batch alkaline texturing, many manufacturing companies areselecting to use acidic texturing for alkaline wafers even though itresults in higher reflectance values. In the case of the described rearcontact cells in the below-mentioned variations 3 to 5, where a rearanodic aluminium oxide layer is employed for enhanced light trapping,use of acidic textured does not result in significant reduced cell opencircuit current because: (i) much of the light reflected from the frontsurface of the ARC is re-directed back into the cell when the cell inencapsulated into a module; and (ii) the rear surface reflector in thesebelow-mentioned variations provides for enhanced light trapping forlight not absorbed in its first pass through the cell.

Lift-off can be achieved with hot melt waxes by simply heating thewafers to temperatures sufficient to melt the wax (e.g., ˜80° C.) andthen rinsing in a solvent for the wax. Heat treatments can also beemployed to assist lift-off for some resins. In these cases it isadvantageous to ensure sufficient amounts of solvent are deposited withthe resin to ensure that a sufficient vapor pressure forms during theheating step to initialise the lift-off process. For these approaches,high vapor pressure solvents are preferable.

Lift-off for water soluble polymers to create the isolation openings 460in FIG. 4F is very straight-forward generally requiring only sonicationin deionised water at 20-25° C. for 10-15 mins. Successful lift-off(i.e., 100% of aluminium above the isolation lines) can be achieved foracidic textured surfaces with a single layer isolation pattern eventhough the dried polymer contains ridges at the edges of the line.However, for alkaline surfaces the dried polymer lines, at least at theedges, must be 6-8 μm high for 100% lift-off after 10-15 mins sonicationin deionised water at 20-25° C. In addition, for the alkaline texturedsurfaces the resulting openings in the aluminium layer are in the orderof 150-200 μm and therefore larger than necessary for isolationpurposes. The use of an alkaline texturing process that results insmaller pyramid sizes (i.e., 1-2 μm high pyramids) can reduce therequired polymer line height. Another factor that makes the lift-offmore difficult for alkaline textured wafers is the existence of residualsaw-damage ridges across the wafers. As many manufacturers seek toreduce their saw-damage etching time to reduce silicon wastage, manycommercial-grade mono-crystalline wafers exhibit a wavy ridge patternacross the surface presumably due to residual saw-damage that has notbeen removed before texturing. This surface pattern can make lift-offunreliable (i.e., less than 100%) depending on the angle of theisolation lines with respect to the inherent waviness on the wafer.

However, these issues with wafer surface can always be addressed byadjusting the height and profile of the printed polymer lines. Printingthroughput can be increased by depositing from more than one nozzle at atime. The nozzles can be aligned to be very close to each other so thatthey slightly increase the width of the printed polymer line (i.e.,printed according to an overlapped pattern).

Variation 1

The cell design, depicted in FIG. 1A and described with reference toFIG. 2, involves etching grooves in the heavily-doped n-type and p-typeregions of the cell. Variations are possible where point contactopenings can be formed in these regions using the patterning approachessuch as described in the PCT publication WO 2011/017740(PCT/AU2010/001001) entitled “A method for the selective delivery ofmaterial to a substrate”. Point-contacting schemes have the advantage offurther minimizing the metal-silicon contact area and there is littleoverhead in forming the point contacts with the designs depicted in FIG.1A and FIG. 1B because the deposition path for the fluoride source canbe directed at an angle (e.g., 90 degrees) to that used to deposit thePAA. In this case, etching only occurs at points where both PAA and thefluoride source have been deposited. This means that point contactschemes can be achieved with effectively no additional processing. Thispresents key advantages over other point contacting schemes (e.g.,laser-fired contacts and laser-doped point contacts) where either a maskmust be used or individual points of the contacting pattern must beincluded and “visited” by the patterning tool. Because the pointopenings in the dielectric layer directly contact heavily-doped silicon,series resistance losses associated with collection of carriers (e.g.,spreading and contact resistance) is minimized.

Variation 2

FIG. 1B shows a variation of the preferred cell design shown in FIG. 1A.This design has the advantages that: (i) the rear emitter islightly-doped resulting in less Auger recombination in the device; and(ii) the n-type contacts which are responsible for collection of theminority carriers are placed closer to the floating junction thusreducing the path length of the minority carrier electrons in the bulkof the wafer. Under illumination the (front) floating junction becomesforward-biased and electrons collected in the n-type region at thesurface 115 are injected into the p-type base 110 where they mustdiffuse to the n-type contacts. The shorter the distance that they mustdiffuse the lower the probability they will recombine with the majoritycarrier holes. In the extreme, if the n-type contact regions areextended through the wafer until they contact the front surface junctionthen an EWT cell results.

The n-type incursions can be grooves or holes and may extend a variabledistance into the wafer. In the event grooves are used, if the groovesare too deep then the structural integrity of the wafer will becompromised and wafer breakage rates will increase reducingmanufacturing yields.

The n-type incursions can be formed using either a laser or by patternedetching substantially as described above for the preferred arrangement.FIG. 5 depicts a patterned etching process 500 for forming theseincursions which can be performed between steps 205 and 210 of FIG. 5.In order to achieve heavy-doping at least in the base of the n-typegrooves 120, first a masking dielectric of preferably silicon dioxide iseither thermally-grown, deposited using a plasma process such as PECVD,or applied as a spin-on-glass layer in step 505. Other dielectricmaterials, such as silicon nitride, silicon carbide and siliconoxynitride can also be used. Although these layers can densify and losetheir passivation properties during the subsequent diffusion step theyare not required to be part of the final device and so can be sacrificedafter the diffusion process.

The thickness of this masking layer must be carefully controlled (step510) because it will act as a partial diffusion mask in step 210enabling light diffusion in all areas where the mask is present andheavy diffusing where it is absence. For a thermally-grown silicondioxide layer preferably the masking layer is ˜90 nm thick. In Step 515openings are etched as described previously for step 220. The openingscan be grooves (e.g., as depicted in FIG. 1A) or holes as described forVariation 1. The silicon is then etched through the openings,substantially as described for step 225 of process 200 to formincursions of the required depth.

When a phosphorus diffusion process is then performed the areas exposedthrough the grooves will be heavily-doped whilst areas protected by themasking layer will only be lightly doped. The thickness of the maskinglayer can be used to control the doping level of the underlying siliconregions.

In the variation where a laser is used to form the incursions (that areto become heavily-doped), the laser can be used to ablate the maskinglayer and form grooves in the underlying silicon. After laser-grooveformation, then preferably an etch in solution comprising 12-15% sodiumhydroxide is performed for 10-15 mins at 50° C. to remove any siliconthat has been damaged during the laser ablation step. This “grooveetch”, which is substantially the same as that performed for buriedcontact cells, can also thin the masking layer and so any thinningeffects on the mask need to be taken into account when the masking layeris first formed or deposited.

Fabrication of the cell can then proceed substantially as described bythe process flow 200 shown in FIG. 2. Alternatively, for othervariations such as depicted in FIG. 8, incursions are not required to bepatterned for the p-type contacts. In this variation, contact toheavily-doped p-type regions is achieved by laser-doping through andanodic aluminium oxide layer. In this variation, the drive-in stepfollowing the diffusion step 210 does not need to form an oxidationlayer for subsequent patterning.

Variation 3

A key to enabling the use of less expensive silicon substrates for cellfabrication is to well-passivate the surfaces of the devices. Aspreviously mentioned, silicon nitride dielectric layers can result invery low surface recombination velocities at n-type Si surfaces due tothe presence of stored positive charges which induce an accumulationlayer at the silicon interface. In a further variation, a rear-surfacedielectric stack comprising a thin layer of silicon nitride (or silicondioxide, silicon oxynitride, silicon carbide or amorphous silicon) and asubsequent layer of anodic aluminium oxide is used to: (i) furtherimprove the passivation of the rear surface; and (ii) provide enhancedlight trapping in the device.

The dielectric stack is formed by first depositing either a siliconnitride, silicon dioxide silicon oxynitride, silicon carbide oramorphous silicon layer on the rear surface of the device by PECVD asdescribed previously for step 240 of process 200. Alternatively, asilicon dioxide layer can be either grown using a thermal oxidationprocess or also deposited by PECVD. An aluminium layer of thickness 200to 800 nm and more preferably 500-700 nm is evaporated or sputtered ontothe silicon nitride. This layer is anodised substantially as describedin PCT application no PCT/AU2011/000586 entitled “Metal contact schemefor solar cells” to form a porous aluminium oxide dielectric layer. Suchanodic aluminium oxide (AAO) films formed over an intervening siliconnitride, silicon oxynitride or silicon dioxide layer can enhance theformation a surface accumulation layer for n-type silicon and result inimproved passivation.

The dielectric stack can be patterned as described for step 245 ofprocess 200 except for the requirement to deposit additional layers ofthe fluoride source in order to etch the thicker dielectric layer. Thedescribed method of patterned etching can also be used to etch layers ofAAO. Although the dielectric stack is thicker than the silicon nitridelayer used for the preferred arrangement shown in FIG. 1A, the amount offluoride ion required to etch the anodic aluminium oxide layer isproportionally less because of the high resulting porosity of the layer(˜10% when the layer is anodised using 0.3 M sulphuric acid and ananodisation voltage of 25 V).

After patterning, metallization can proceed as per steps 250 to 260 ofprocess 200. As the aluminium is deposited it fills the pores in the AAOas shown in FIG. 6 forming a metal-dielectric structure 620 between thedeposited aluminium (610) and intervening silicon-based dielectric (630)that acts to scatter transmitted light back into the cell forabsorption. The metal structures in the dielectric serve to couple thelight back into the cell at oblique angles which increases the length ofthe light path and hence the probability of absorption. This lightscattering property is advantageous in minimising transmission of lightout from the rear surface of the cell in the narrow isolation pathregions (i.e., where the rear metal electrode has been removed forisolation purposes using the previously described lift-off method).

Variation 4

A further variation of the preferred arrangement is depicted by theprocess flow 700 in FIG. 7 and FIG. 8. In this variation the ability ofan AAO layer to provide a source of aluminium atoms to heavily-dope thecontact regions is exploited. The process 700 proceeds as described forprocess 200 until the p-type grooves are etched in step 225. Instead ofperforming the heavy p-type doping at this stage the oxide is removed asdescribed for process 200 in step 235, and then in step 705 the Si-baseddielectric of choice (e.g., silicon nitride) is applied to both thefront and rear surface of the cell. A different Si-based dielectric canbe used for the front and back surface, and the thickness of the layercan be varied between the two surfaces. Preferably the thickness of thefront surface layer is maintained at ˜75 nm for the dielectric having arefractive index of ˜2.0 to minimize reflection from that surface.

An AAO layer 820 is then formed over the entire rear surface in step 715as described for Variation 3. A laser can then be used to locally-meltand thus heavily-dope the silicon at the base of the grooves in step720. The presence of the grooves can be clearly identified in analignment camera attached to laser, with both point and line alignmentbeing performed to ensure that the laser path follows the patternedgrooves. A high powered 532 nm laser may be used to perform the dopingstep. The laser scanning speed may be between 0.1 and 2 m/s, andpreferably between 0.5 and 0.6 m/s to minimise formation of defects andto maximise doping in the laser-doped lines. The sheet resistance at thebase of the laser-doped grooves is preferably 10-45 Ω/sq, and morepreferably 15-25 Ω/sq.

The formation of the p-type heavily-doped regions 810 using local dopingfrom the AAO layer 820 is advantageous because it means that the bulk ofthe wafer is not exposed to high temperatures which can potentiallydegrade the minority carrier lifetime and ultimately the performance offinal devices. Optionally, an annealing process can be included afterthe laser-doping step (step 720) to anneal any damage which may haveoccurred during the laser-doping step. Preferably this annealing is doneunder forming gas (e.g., 4% H₂ in N₂ or Ar) at a temperature between 350and 700° C. and more preferably between 650 and 680° C.

In step 725 openings can be formed to the heavily-doped n-type silicon140 using the patterned etching process previously described for step245 of process 200. The thus patterned rear surface can be metallised asdescribed for process 200.

The local doping process can be varied by filling the pores of theporous layer 820 with a material that can alter the resulting localdoping of the underlying silicon. For example, a material representing asource of boron atoms such as boric acid can be used to fill the poresbefore the laser-doping in step 715. Addition of boron dopant atoms inthe locally-doped silicon can increase the conductivity of the dopedregions 810 and reduce the contact resistance.

Although the process 700 requires further processing equipment (e.g., alaser) and hence a slightly more complicated process, it has a number ofadvantages. First, by using a local doping technique the wafers are notsubjected to a high temperature process to enable the local p+ doping.This enables lower-quality wafers potentially to be used. Furthermorethe AAO, which provides a source of dopant atoms for the local p+doping, also provides enhanced rear-surface passivation andlight-trapping properties which enables higher cell efficiencies to beachieved for a similar cost of processing.

Variation 5

The AAO dielectric structure can be used for alternative cell designssuch as depicted in FIGS. 9 & 10 which are a variation of the celldesign depicted in FIG. 1B. The process flow 900 shown in FIG. 9 is usedto fabricate this alternative cell design. In this variation the processproceeds as described for process 500 to result in a masking oxide layerwhich results in heavily-doped n-type regions at the exposed bases ofthe rear surface grooves after the diffusion process in step 910 and thedrive-in oxidation (step 215) which is performed as described for theprocess 200. As an oxide layer is not required for subsequent patterningas described for process 200, the drive-in process does not need toresult in the formation of an oxide layer. Alternatively, as describedwith respect to Variation 2, groove or point incursions can also becreated using a laser.

The masking oxide is then removed in step 235 and the rear dielectriclayer, preferably comprising a Si-based dielectric 125 and an AAO layer810, is formed as described for process 700. Heavily-doped contact tothe base of the cell 1000 can be formed by using the laser to patternand simultaneously dope through the rear dielectric layer formingheavily-doped p-type regions 1010 at the rear surface. The rear surfaceemitter is relatively lightly-doped resulting in sheet resistancesbetween 100 and 500 Ω/sq and more preferably 150-200 Ω/sq on the rearsurface after the diffusion process in step 910, and so minimal shuntingoccurs between the n-type rear surface emitter and the subsequentlyformed p-type metal contacts. The process then continues as describedfor process 200.

Fabrication processes such as described for Variation 5 are advantageousfor very thin substrates such as made possible by lift-off methods whereultra thin silicon cells are released onto and supported by flexiblesubstrates. In these processes typically the structuring (i.e.,patterning of diffused areas) for the cell is performed whilst thesilicon is supported by a re-useable substrate. The patterned cells canthen be released onto a flexible substrate and be interconnected toother similarly thin patterned wafers to form a flexible module. Inthese variations the presence of the AAO layer provides enhanced lighttrapping which is critical for such thin wafers.

Variation 6

The p-type metal contacting scheme described above with respect to FIG.9 and FIG. 10 can also be applied to cell designs having a front surfacen-type emitter and front-surface n-type metal contacts, for example asemployed by standard screen-printed solar cells and the many variants ofselective-emitter silicon solar cells that are currently beingmanufactured. In this variation there is no need for the rear-surfacepatterning processes associated with the n-type contact because thesecontacts are now formed on the front (illuminated) surface of the solarcell. Although cell designs such as these experience shading losses dueto the presence of the front metal contacts, the front-surface emitterprovides for efficient capture of minority carriers because thesecarriers no longer need to traverse the effective width for the cell forcapture. Consequently lower-quality wafers can be used thus reducing themanufacturing costs and yielding lower $/W manufacturing.

The device shown in FIG. 11 has a front surface emitter 1120 and anoptional a rear surface floating junction 1115. The front contactstructure comprises heavily doped contact regions 1140 and metallisation1150 formed by conventional methods, including opening the dielectriclayer 125, doping the silicon under the opening to form the heavilydoped n-type region 1140 using diffusion or laser doping methods andplating or screen printing the metal contacts 1150. In other respectsthis variation is similar to the arrangement of FIG. 8 and includes thedielectric stack 126, 125, 820 similar to that illustrated in FIGS. 6 &8 and the rear p-type contact structure comprising heavily-doped p-typeregions 1130 contacted by the rear surface metallisation 150 throughholes 1145 in the dielectric stack 126, 125, 820. The grooved structureof the earlier embodiments is not required in this instance because thecell has a front surface emitter 1120.

The device depicted in FIG. 11 has advantages over existingscreen-printed or laser-doped selective emitter cells in that the rearsurface is well passivated by a dielectric stack containing an AAO layerat all regions except where local contacts 1145 are made to the metallayer 150. This local contacting results in higher open circuit voltagesdue to reduced recombination at the rear surface. Additionally the AAOlayer 820 enhances light trapping in the device thus enabling thinnersilicon wafers to be used.

Variation 7

In a final variation, patterns of metallic and insulating/light trappingregions can be formed on a rear surface by patterning a layer ofaluminium before anodisation. The patterning can be performed using the“lift-off” method described in process 200. If regions of the aluminiumlayer are isolated from those aluminium regions contacted by the anodicvoltage, then they will remain metallic whilst those regions that aremade anodic will form local AAO regions. The isolation of regions of analuminium layer can also be achieved using the patterned etching methoddescribed earlier for steps 220 and 245 of process 200.

This variation is advantageous in that it enables metal contacting,passivation and light trapping to be achieved using a single layer ofaluminium. Furthermore, heavily-doped aluminium regions can be formedthough openings by firing the patterned aluminium layer after theanodisation process. Anodic aluminium oxide layers can resisttemperatures in excess of typical aluminium firing temperatures of 800°C. and consequently can support the formation of aluminium alloyedregions in the metallic regions.

Light trapping in these partially anodised surfaces can be enhanced byfilling the porous AAO with dyes that can absorb and re-emit light thatescapes from the rear surface of the cell. Alternatively the pores canbe filled with reflective materials such as colloids of titanium dioxideparticles or similar nanoparticle preparations. These dyes or reflectivenanoparticles can be incorporated into polymers used to encapsulate thecells in a module.

This variation can be applied as a rear contact scheme for a cell designsuch as depicted in FIG. 11 where n-type metal contacts 1150 are formedon the (front) illuminated surface of the cell. Patterned openings canbe made to the p-type base of the cell using any of the patterningapproaches described for the above variations. Preferably the openingsare made to heavily-doped p-type regions to ensure ohmic contacts. Alsoit is desirable that the area of the silicon exposed via these openingsis minimised to reduce recombination at the metal silicon interface.Line or point openings can be made through a dielectric layer, such assilicon nitride, silicon oxynitride, silicon carbide or amorphoussilicon.

A single aluminium layer can then be patterned into metallic andinsulating regions using isolating techniques described from process200. A rear surface 1200 of a cell represented by the schematic in FIG.11 to which this variation is applied is shown in plan view in FIG. 12and a sectional elevation view of a part of the cell is shown in FIG.14. The dashed lines 1220 represent arrays of point openings that havebeen formed through a rear dielectric layer such as silicon nitride. Alinear isolation line 1250 is then deposited as described for step 250in process 200. The line isolates the region 1210 (i.e., between thelinear arrays of openings) from the region 1240 which overlies theopenings 1220 in the dielectric layer 125. A layer of aluminium 150 isthen deposited over the entire rear surface and “lift-off” is thenperformed as described in step 260 of process 200 in order to patternthe aluminium layer in to two electrically isolated regions, one ofwhich is subsequently anodized, resulting in the anodized region 1260and the aluminium contact region 1240 as shown in FIG. 13. A sectionalelevation of the cell after anodising and contact doping is shown inFIG. 15.

In order to improve the passivation and light trapping over the region1210, which does not contact underlying openings in the dielectriclayer, that region is connected to the positive terminal of a powersupply and anodised as described for step 715 of process 700. Thisresults in the formation of a rear insulating region 1260, that improvesboth the minority carrier lifetime and light trapping properties of thedevice. The creation of this insulating region 1260 does not affect themetal region 1240 because it has been isolated from the metal region1210 during the anodisation process. The metal region 1240 can thereforefunction as the rear metal electrode for the solar cell.

This patterning of a single aluminium layer 150 into both a metal region1240 and an insulating region 1260 can also be achieved by printing anetchant for the aluminium according to the pattern 1250. Etchants suchas heated phosphoric acid can be readily deposited using printingdevices such as inkjet or aerosol printer, however care must to be takento ensure the etchant does not detrimentally affect the underlyingdielectric layer (e.g., silicon nitride).

In another variation, the need to separately form openings through thedielectric layer (such as the linear array of point openings depicted by1220 of FIG. 12) is eliminated. In this variation, a thin silicondioxide layer can be formed over the entire rear surface. Preferably thethickness of the silicon dioxide layer is between 10 and 70 nm thick andmore preferably 15-30 nm thick. The isolating line 1250 can then beprinted such that it results in narrow fingers in the region 1240 afterlift-off. Following the anodisation step to create the insulation region1260, the cell can be fired as described previously to create aluminiumalloyed regions 1530 under the metallic region 1240 (see FIG. 15). Thisvariation eliminates the requirement to deterministically form openingsthrough the dielectric layer to the heavily-doped p-type silicon.Alternatively, the silicon dioxide layer 126 can be replaced by a thinamorphous silicon layer of thickness between 10-50 nm, and morepreferably 10-20 nm thick. When aluminium is deposited over theamorphous silicon and heated to temperatures below the eutectictemperature of the silicon-aluminium alloy, silicon and aluminiuminterdiffuse and on cooling the silicon surface becomes heavily-dopedwith aluminium. This represents another way in which aluminium contactto heavily-doped regions can be achieved without the need to directlyform openings in the dielectric layer. The AAO region 1260 can be formedover the intervening silicon dioxide and amorphous silicon as describedpreviously for silicon nitride intervening layers.

As seen in FIGS. 16 & 17 this patterning variation can also be appliedto rear contact cells similar to those seen in FIGS. 4A & 4B where metalcontacts for both polarities are formed on the rear surface. Isolationpatterns which isolate each of the metal electrode regions (of differentpolarities) from the insulating region can be formed with the width ofisolation trenches being as narrow as 100 μm.

Variation 8

Referring to FIGS. 18, 19, 20, 21 & 22 patterns of metallic andinsulating/light trapping regions can also be formed from a single layerof metal 1850 by masking regions of the metal layer to remain metallicduring the anodising step so that the anodising electrolyte does notcontact the masked regions. The metal layer 1850 will preferably bealuminium and the examples described herein will be described with treference to aluminium but other metals such as titanium, magnesium,zinc, and more precious metals such as niobium and tantalum can also beused to form the metal layer.

Referring to FIG. 18, the aluminium layer 1850 is seen covering the backsurface of the device 1800 and contacting the heavily doped p-typeregions 1010 and the heavily doped n-type regions 1820 which are formedby traditional methods such as diffusion or laser doping andrespectively provide semiconductor contact regions for the more lightlydoped p-type region 110 and the more lightly doped n-type region 120 ofthe solar cell.

Now turning to FIG. 19 selective masking of regions of the aluminiumlayer 1850 can be achieved by first forming a layer of acid resistantmaterial (resist) 1865, such as novolac resin, over the entire surfaceof the aluminium layer 1850 and then selectively removing or modifyingthe resist 1865 in the regions 1870 where anodisation is required byprinting or depositing a fluid that either removes the resistantmaterial or makes it permeable to the acidic electrolyte that willsubsequently be used to anodise the metal regions under the resistregions 1870. For resins, such as novolac resin, alkaline solutions suchas potassium hydroxide or sodium hydroxide can dissolve and hence removeresist regions. These caustic solutions can be inkjet printed usingalkaline resistant printheads such as provided by Konica Minolta, ordeposited using an aerosol printer where the solution does not contactand hence damage the deposition tip surface.

Alternatively, resists such as novolac resin can, be made permeable toacid solutions by depositing a plasticiser for the resist, substantiallyas described in US patent application 20100047721. An advantage ofsimply making the regions 1870 of resist permeable to the acidelectrolyte is that this permeability can be reversed, thus enabling thelayer of acid resistant material to form a component of the finaldevice. Resin layers can be formed with light scattering and/orreflective particles.

After the resist is processed, it will be as seen in FIG. 20 in whichintact resist regions 1866 mask the n-type contact metal and intactresist regions 1867 masking the p-type contact metal. The areas 1870between the intact resist areas 1866 & 1867 will either be removed ormade permeable to allow anodising to proceed in those areas.

Regions of the dielectric layer can be selectively etched using themethod described above for step 220 of process 200. Referring to FIG.21, after the anodisation process is complete, the aluminium exposed tothe anodising solution will be converted to one or more porous oxideregions 1875 which separate the remaining regions of the aluminium layer1850 into two different contact regions, a first of which becomes ap-type contact metal region 1856 contacting the p-type semiconductorregions 1820 and the other becomes an n-type contact metal region 1857contacting the n-type semiconductor regions 1010.

In the case where the resist is made permeable in the regions 1870 whereanodisation was required, after the anodisation process is complete, theregion of resin with colloidal particles 1870 can be reflowed to fillthe formed pores in the formed AAO regions 1875 providing an enhancedrear reflector for the solar cell device 1800. The reflow processdescribed in US patent application 20100047721, involving exposing theresistant material to a saturated vapour of the solvent for the resin(e.g., propylene glycol methyl ether acetate for novolac resin), can beused for this purpose.

Selective masking of regions of the aluminium layer 1850 can also beachieved by depositing a masking layer 1865 of an inorganic materialsuch as silicon dioxide, titanium dioxide, aluminium oxide, siliconnitride, silicon oxynitride and silicon carbide, and then selectivelyetching regions of this layer to expose the surface of the aluminiumlayer 1850 in the regions 1870 or else by directly depositing these orsimilar masking materials to protect the metal regions 1856 & 1857 thatare not to be anodised. These masking dielectric layers are preferablydeposited by PECVD, however other deposition methods such as sputteringor annealing of spin-on-glasses, or localised deposition of the maskingmaterial such as by inkjet or screen printing, can be used. Preferablythe masking layers are 5 to 100 μM thick and more preferably 60-80 μmthick.

Regions of the dielectric layer can be selectively etched as above usingthe method described above for step 220 of process 200.

Once the anodisation process has been performed the inorganic dielectricmask can be removed by immersion of the device in an etchant for thedielectric material used for a short time. Because the masking layer ismuch thinner than the formed AAO regions, it can be removed withoutsignificantly etching the formed AAO regions.

Patterns of acid resistant material 1866 & 1867 can also be formed bydirectly printing or depositing the resistant material over thoseregions of the aluminium layer 1850 which are not to be anodised (i.e.,required to remain metallic). The resistant material can be deposited asdescribed earlier for the isolating resin lines. Alternatively it can bedeposited using other printing methods such as screen-printing or inkjetprinting. The regions of the aluminium layer 1850 not exposed by theacid resistant material will then be anodised, whilst those regionsprotected by the resistance material will remain metallic.

This selective anodisation process can also be used to electricallyisolate the n-type and p-type electrodes on the rear surface of devicessuch as depicted in FIGS. 1A, 1B, 8 and 10 (FIGS. 18, 19, 20, 21 & 22depict an arrangement similar to that of FIG. 10). Instead of printingisolation lines, as described for the previously described arrangements,masking regions can be formed over the metal regions overlying thecontact areas for each of the n-type and p-type contacts. The maskingregions can be formed by printing a polymer as described previously forthe printing of the polymer lines (step 250 of process 200). FIG. 22shows the rear surface of a solar cell 1800 where polymer regions 1866 &1867 have been printed on the aluminium surface 1850 overlying then-type semiconductor contact regions 1010 and the p-type semiconductorcontact regions 1820.

The width of the protected regions 1866 & 1867 can be varied to suit therequirements of the device and the method of extracting the current fromthe device. For example, in order to extract the current from acommercial-sized rear contact cell it is preferable for the resultingaluminium electrode to form a seed layer and that metal platingprocesses be used to thicken this seed layer to reduce the resistance inthe metal grid. In this case it is, not necessary for the metal fingers1856 & 1857 to be very wide if 20-30 microns of electroplated copper canbe used to thicken the metal grid.

After masking the electrode regions 1866 & 1867 on the rear surface therear aluminium surface 1850 can be anodised to form an AAO 1875 in theunmasked regions only, which simultaneously passivates the underlyingsilicon surface in these regions while electrically isolating the metalcontact regions 1856 & 1857 of the two semiconductor polarities 110 &120. After removal of the masking polymer by dissolution in a solvent(e.g., acetone), the electrode regions 1856 & 1857 can be thickened by aplating process. It is difficult to electroplate directly to analuminium surface, so for this reason preferably a thin zinc layer isformed over the aluminium surface in a process called “zincating”. Inthis immersion plating process a surface layer of aluminium iseffectively exchanged with a thin zinc layer from a solution of zincions. Zinc is less prone to oxidation than aluminium and hence can beused as a seed layer for a subsequent electroplating process.

During the electroplating process metal (e.g., copper) only plates tothe metallic electrode regions 1856 & 1857 of the rear surface and doesnot plate to the insulating AAO regions 1875. Using electroplating toolsthe rear grid lines can be thickened to be 20-30 μm thick thus ensuringthat fractional power losses due to series resistance losses aremaintained below 3% and preferably below 1%. After the metallisationprocess, the pores of the AAO 1875 can be filled with a reflectivefiller to enhance the light trapping properties of the insulatingregions. The filler can be provided as previously described as part ofthe rear encapsulating material or the resist material 1870 that wasmade porous for the anodising step may be used.

A simple variation of the interdigitated contact approach above is toapply it to thin crystalline silicon layers whereby seriesinterconnected devices are formed by having the n-type metal from onecell directly contacting the p-type metal contact from the adjacentcell. Again, both metal contacts including the series interconnection,plus the surface passivating AAO in non-metallised areas, are all formedfrom the one deposited layer. Electrical isolation through thesemiconductor material between adjacent devices is relatively easy toachieve when using thin silicon layers of thickness in the range 1-30microns. Such layers are not self supporting and therefore have to beprocessed when bonded to a supporting substrate or superstrate such asglass, increasing the importance of using the described approaches thatfacilitate single sided processing for both polarities of metal contact.

A further variation of the above is where only the n-type contact inFIG. 22 is formed in the described manner, while the p-typeinterdigitated contact is subsequently formed by using a laser to scanthe region where the p-type contact is to be formed as described for theFIG. 8 variation. The scanning of the laser can be used tosimultaneously pattern the AAO layer while using the Al from the AAOlayer as a p-type dopant source such that melting the underlying siliconsurface allows the Al to be incorporated into the silicon surface toproduce an exposed P+ surface in preparation for self-alignedmetallisation such as by plating. Such laser doping and self-alignedmetallisation processes are well documented elsewhere but with theadvantages in this implementation being that firstly the passivatinglayer provides the dopant source and secondly, the structure of thepores in the AAO layer provide a stress release mechanism that minimisesthe defect generation within the silicon that is common in suchprocesses due to the thermal expansion coefficient mismatch between thesilicon and the overlying dielectric. As previously, following theformation of the interdigitated contacts as described, the remaining AAOlayer provides excellent electrical isolation between the two polaritiesof contacts while also providing excellent surface passivation and alsopotentially excellent light-trapping in the non metallised regions.

Although this approach has obvious benefits when forming interdigitatedcontacts of both polarities on the same surface of the wafer or layer ofsemiconductor, it can similarly be applied to forming a metal contact ofeither polarity on either surface. For example a wafer with an n-typeemitter on the top surface and p-type exposed rear surface of the wafer,can use this approach to form localised n-type contact to the topsurface and localised p-type contact to the rear surface by depositinglayers of Al onto both surfaces, masking the respective regions thatwill form the metal contacts, and then simultaneously anodising theremaining unmasked Al on both surface to form well passivated surfacesin the non metallised regions. In this case, the thickness of the topsurface layer of Al can be chosen so that after anodisation, it is theright thickness to be an excellent antireflection coating for the cellthat achieves its minimum reflectance at a wavelength of about 600 nm.In this way, the anodisation process is used to not only perform thepreviously described functions, but also to control the transmission andreflection properties of the deposited layer in terms of which regionsthe light is allowed to pass and with what wavelength bias.

Another example of the implementation of this approach is wherelocalised regions of metal induced crystallisation (MIC) of amorphoussilicon (a-Si) are required. Amorphous silicon is known to provide thebest quality of surface passivation for crystalline silicon but haslimitations in terms of needing to be protected from other materialssuch as metals that can trigger off changes in the a-Si properties. Inthe present approach, an a-Si layer can be used instead of the oxidelayer 126 to passivate the rear surface of a solar cell 1800 shown inFIGS. 18-22 (or indeed devices using this method when employed in theconfigurations described for any of the earlier embodiments describedherein). The rear surface can be coated with a layer of Al which canthen be selectively anodised in regions where the a-Si properties andsurface passivation are to be retained. In the masked regions 1856 &1857 where the metallic properties of the Al are retained, subsequentinteraction between the Al and the a-Si such as by heating to atemperature within the range 150-577 deg C., MIC of the a-Si takesplace, enabling the formation of a heavily Al (p-type) doped crystallineor polycrystalline silicon region 1010 to be formed at the interfacebetween the Al and the crystalline silicon. Such regions form excellentelectrical contact between the remaining Al material and the p-typesilicon surface while simultaneously minimising the dark saturationcurrent contribution from the metal/silicon interface by having suchregions in only localised areas and by using the newly formed p+ regionto shield the interface from the active parts of the device. In thepassivated regions, the AAO layer 1875 provides an excellent protectivebarrier to preserve the properties of the underlying a-Si layer duringsubsequent metallisation, exposure to various environments andeventually to encapsulation processes and the associated materials usedfor these purposes. Importantly, the AAO layer can also be used toprovide light-trapping for the device as previously described or else bydeliberately sizing the pores so that they can be coated duringencapsulation or separately, so as to trap air within each pore. Thegeometry of these pores combined with the excellent transmissionproperties of the AAO combined with the large percentage of lighttotally internally reflected at the interface with the trapped air,potentially provides both excellent internal reflection within thesilicon as well as excellent light-trapping. An example implementationof this approach is as follows:

-   -   1. texture p-type wafer surfaces    -   2. top surface diffusion with phosphorus    -   3. rear surface etch to expose p-type rear surface    -   4. PECVD of 75 nm of SiNx on front surface at 400 deg C.    -   5. PECVD of 30 nm amorphous silicon onto the rear surface at 200        deg C.    -   6. Application of phosphoric acid onto front surface followed by        laser doping in regions where metal contact formation is        required    -   7. Sputtering or evaporation of aluminium layer onto the rear        surface over the a-Si    -   8. Inkjet deposition of masking material in regions to form the        rear metal contact    -   9. Anodising process to convert non masked regions of the Al        layer into anodic aluminium oxide AAO    -   10. Removal of masking material    -   11. Thermal treatment at 500 deg C. for 10 minutes for MIC of        the a-Si beneath the remaining Al to produce self-aligned p+        silicon at the metal/Si interface    -   12. Light induced plating of Ni onto the exposed n-type laser        doped regions    -   13. Ni sintering at 375 deg C. for 3 minutes    -   14. Light induced plating of Cu and silver onto the Ni seed        layer

Another powerful use of selectively anodising regions of the Al layer isto electrically interconnect separate devices formed on the samesubstrate. For example, the large majority of a silicon wafer can beused as a solar cell while a small region can be used for the formationof other semiconductor devices such as diodes, transistors, thyristors,resistors and capacitors. Combinations of such devices can be used toform a range of useful circuits such as for the purpose of forming abypass diode, blocking diode, voltage regulator, maximum power pointtracker, DC to DC converter etc. This is not a new concept and suchdevices can be formed by localised laser doping or masked diffusionsetc, but the challenge has always been to find a simple, reliable andlow cost way of interconnecting such devices. The present approach ofselective anodisation of Al layer allows such device interconnection tooccur from the single layer of Al that both interconnects all thedevices as required while allowing the anodised regions to provide bothpassivation of all the non-contacted regions of all devices andexcellent electrical isolation between such devices. The outcome isequivalent to the use of a printed circuit board for the interconnectionof electronic devices except that in this implementation, it is formedin a simple, reliable, low cost manner that is compatible with theformation and operation of a solar cell.

The method of selective anodisation described in Variation 7 andVariation 8 can be applied more generally to solar cell manufacturewhere a single layer comprising both conductive and insulating regionsis required. As has been described this can be achieved by either:

-   -   (i) forming the required pattern in the conductive metal layer        and then only electrically contacting the regions to be anodised        (i.e., as described in Variation 7); or    -   (ii) by masking regions of the conductive metal layer that are        to remain conductive with an acid resistant material so that the        underlying metal does not contact the anodising electrolyte        (i.e., as described for Variation 8).        Variation 9

Referring to FIG. 23, an AAO pattern can be formed on a surface of asubstrate 110 of a solar cell 2300 by the printing of an aluminium ink2350 comprising a colloid of aluminium particles in a solvent,optionally over a dielectric layer 2326, such as silicon nitride. Theink can be deposited using a printing device such as an inkjet printer,aerosol printer or a screen printer. Depending on the printing device,the viscosity of the solution can be varied by altering the solvent.Inkjet printing requires the use of a low-viscosity solvent such asethylene glycol, whereas higher viscosity solvents can be used foraerosol or screen printing. Preferably the aluminium particles in thecolloidal ink are capped with an organic capping layer to minimiseoxidation of the aluminium.

Aluminium colloidal inks, such as provided by companies such as AppliedNanotech can be readily deposited using a pneumatic atomiser of anaerosol printer as described previously. Preferably the particles areless than ˜2 um in diameter to ensure reliable and sustainedaerosolisation. Wide area aerosol deposition heads, which can depositover linear regions that are 0.5 to 3 cm wide and more preferably 1-2 cmwide, can be used to increase the throughput of the deposition processand printing speed can be used to control the thickness of the depositedaluminium layer. Once printed, the aluminium layer is sintered at atemperature between 150 and 500° C., and more preferably ˜200° C. toremove the capping layer from the particles and form a conductive metalfilm 150 (see FIG. 24) which can be anodised as described previously.Unlike Variations 7 and 8 where a pattern of metallic and insulatingregions are formed of the surface by selective anodisation, thisvariation results in a pattern of AAO regions on the surface.

Forming a pattern of AAO on selected areas of a surface can be desirableif aluminium is not the preferred silicon contacting metal. For example,referring to FIG. 25, corrosive nickel inks can be printed to firethrough the dielectric layer 2326 (e.g. silicon nitride), to form a seedlayer 2550 for plated metal contacts 2650 (see FIG. 26) that lie withingaps in the AAO pattern 2660 to contact the p-type semiconductor contactregion 2330 and the n-type semiconductor contact region 2320. Thecorrosive nickel inks may be applied before the anodising step and firedwhen firing the printed aluminium ink 2350. Alternatively the corrosivenickel inks may be applied after the anodising step. During a subsequentplating process the AAO regions form a plating mask and can be used torestrain the lateral growth of plated metal deposits 2650.

Alternatively the aluminium ink can be deposited over the entire surfaceof the solar cell to form a conductive metal layer and then selectivelyanodised as described for the previously mentioned variations. Thismethod of forming the conductive aluminium layer has advantages overthermal evaporation and sputtering which involve vacuum processes andresult in metal wastage as metal deposition cannot be limited to justthe cell area.

The invention claimed is:
 1. A method of forming an electrical contactfor a solar cell device, the method comprising: a) depositing polymerlines on a surface of the solar cell device; b) forming a metal layerover the polymer lines and the surface of the device; c) performing aprocess to lift-off portions of the metal layer formed over the polymerlines to form a plurality of isolated regions in the metal layer; and d)selectively anodizing the isolated regions of the metal layer to provideat least one insulating region and at least one metal region, wherebythe at least one metal region forms the electrical contact of the solarcell device.
 2. The method of claim 1 wherein the polymer is depositedusing a printing method comprising one of screen printing, inkjetprinting or aerosol printing.
 3. The method of claim 1 wherein an anodicpotential is applied to a subset of the plurality of isolated metalregions during the selective anodizing, resulting in the at least oneinsulating region and the at least one metallic region.
 4. The method ofclaim 1 wherein the selective anodizing step forms a plurality of metalregions separated by the at least one insulation region.
 5. The methodof claim 4 wherein the solar cell device is a rear contact solar celldevice and at least one of the plurality of metal regions contacts ap-type semiconductor region of the solar cell device and at leastanother one of the plurality of metal regions contacts an n-typesemiconductor region of the solar cell device.
 6. The method of claim 4wherein the solar cell device comprises a plurality of photovoltaicdevices, and at least one of the metal regions is in contact with ap-type semiconductor region of the solar cell device and a n-typesemiconductor region of an adjacent solar cell device to create a seriesconnection of the adjacent solar cell devices.
 7. The method of claim 1wherein the metal layer comprises aluminium, titanium, magnesium, zinc,tantalum, or niobium.
 8. The method of claim 1 wherein the metal layercomprises aluminium.
 9. The method of claim 1, wherein the polymer linescomprise novolac resin dissolved in a high vapor pressure solvent. 10.The method of claim 9, wherein the solvent is sulfolane and the resin isdissolved at a concentration of 1 to 12% (w/v).
 11. The method of claim1, wherein the height of the deposited polymer lines is less than 2times the thickness of the metal layer.
 12. The method of claim 1,wherein the height of the deposited polymer lines is at least 5 timesthe thickness of the metal layer.
 13. The method of claim 1, wherein thepolymer lines are water soluble and the processing of the device tolift-off the metal above the polymer lines comprises dissolving thepolymer lines using water.
 14. The method of claim 13, wherein the watersoluble polymer lines comprise polyacrylic acid.
 15. The method of claim13, comprising sonicating the polymer lines in a water bath.
 16. Themethod of claim 1, wherein the processing of the device to lift-off themetal above the polymer lines comprises melting the polymer lines. 17.The method of claim 16, wherein the polymer lines comprise a wax.